Digital Design Engineer (m/f/d) - REF6693T at Aumovio in Frankfurt | EnJobs

Digital Design Engineer (m/f/d) - REF6693T at Aumovio in Frankfurt | EnJobs

Job details

Company

Aumovio

Location

Frankfurt, Germany

Employment type

Full-time

Seniority

Mid level

Primary category

Electrical & Electronics Engineering

Posted date

30 Mar 2026

Valid through

29 May 2026

Job description

Architect, design, and verify complex digital front-end circuits and systems for FPGA and ASIC implementations, including defining digital design requirements, developing architectural specifications, and coding high-quality HDL modules that meet performance, reliability, and scalability targets
Execute all assigned tasks with strong focus on reusability, efficiency, and area-optimized design
Lead/participate in comprehensive design reviews, providing clear, constructive feedback to enhance design robustness, quality, and development efficiency
Apply mixed-signal understanding (is a strong plus) to ensure smooth integration of digital front-end architectures with analog and mixed-signal components
Proactively define optimal system and component-level concepts, driving digitization initiatives in close collaboration with engineers from all relevant disciplines
Collaborate with cross-functional engineering teams (eg. application and system engineers) to establish cost-effective solutions that meet functional, performance, and architectural objectives
Provide technical guidance and mentorship during reviews and technical discussions, contributing to a culture of engineering excellence
Continuously refine and enhance digital design methodologies, development workflows, and toolchains to increase productivity and design consistency
Create and maintain comprehensive digital design documentation, including requirements, architecture descriptions, design specifications, and block-level details
Develop, execute, document and/or review design processes, verification strategies, test plans, and results in compliance with industry standards and best practices
Build SystemVerilog/UVM-based testbenches and reusable verification components