Monolithic聽Power聽Systems,聽Inc.聽(MPS)聽is聽one聽of聽the聽fastest聽growing聽companies聽in聽the聽Semiconductor聽industry.聽We聽are聽worldwide聽technical聽leaders聽in聽Integrated聽Power聽Semiconductors聽and聽Systems聽Power聽delivery聽architectures.聽At聽MPS,聽we聽cultivate聽creativity,聽are聽passionate聽about聽sustainability,聽and聽are聽committed聽to聽providing聽leading-edge聽products聽and聽innovation聽to聽our聽customers.聽Our聽portfolio聽of聽technology聽helps聽power聽our聽world聽---come聽join聽our聽team聽and聽see聽how聽YOU聽can聽make聽a聽difference.
Job Description:
A **Sr. DFT Engineer **leads the end-to-end design, implementation, verification, validation and debugging of Digital and Mixed-Signal ICs DFT architectures and solutions utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions. 聽
MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.聽
**Essential Functions:聽**
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Development and implementation of DFT Architectures and Techniques.
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RTL Design, debugging and Verification.
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Physical implementation, debugging and Gate-Level Verification.
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Generation of High-Quality Test and Debug Patterns.
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STA and Power Analysis of DFT Modes.
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Silicon bring-up, support, failure analysis, backtracking and diagnosis. 聽
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Synthesis: timing, input/output and DFT constraints definition. Results and Reports analysis.
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LEC: constraints definition and debugging. Results and Reports analysis.
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ATPG Generation and Simulation.
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Analog, Digital and Mixed-Signal AMS Verification support.
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Close interaction with other Departments (Analog, Testing, Product, Digital).
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Analog and Digital Functional Testing.
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Test Plan Definition for Analog and Digital Structural and Functional Testing.
聽**Qualifications:聽**
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BSEE + 15 years of experience, MSEE + 12 years of experience as a DFT Engineer.聽
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Has the ability to work independently and collaborate with other teams or departments.
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Solid knowledge of the full ASIC development process.
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Excellent RTL Verilog or System Verilog coding skills.
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Knowledge of standard Digital Verification languages (SystemVerilog/UVM) and Gate-Level Sims.
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Experience with Standard and Advanced DFT Techniques (ATPG, SCAN, IDDQ, Delay Fault, SCAN Compression/EDT, Reduced Pin Count SCAN, Boundary SCAN, LBIST, MBIST, ABIST, JTAG, etc.).
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Proficiency with ATE implementation, debugging and failure backtracking.
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Excellent understanding of Trade-Off between Test Quality and Test Time.
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Very good understanding of the backend flow: Synthesis, P&R, DFT, Power, LEC and STA. 聽 聽 聽 聽 聽 聽 聽 聽
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Excellent written/verbal communication skills and strong team work/collaboration. 聽
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Knowledge/Experience with the following is a plus:聽 Automotive standards
Knowledge of power management industry/applications聽
I2C, I3C, SPI, USB, PMBUS, ARM and/or RISC-V designs
Scripting and automation languages like TCL, Phyton and C/C++
- ASIC tool knowledge(Cadence, Synopsis) and DFT tool knowledge(Modus, Tetramax, Testsent Fastscan/TestKompress, TestInsight, etc)
**Location: 聽**Barcelona, Spain聽
Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.